Method and system for dynamic FIFO flow control

ABSTRACT

Method and system for a dynamic FIFO flow control circuit. The dynamic FIFO flow control circuit detects one or more obsolete entries in a FIFO memory, retrieves the address of the next valid read pointer, and reads from the retrieved address during the next read operation.

BACKGROUND OF INVENTION

[0001] 1. Field of Invention

[0002] The present invention relates generally to computer systems. Moreparticularly, the present invention relates to a flow control circuitcapable of dynamically detecting and avoiding obsolete data entry readoperations in a First In First Out (FIFO) memory.

[0003] 2. Related Art

[0004] Data transfer in most computer systems is typically conductedbetween a sending element and a receiving element according to ahandshake protocol. In computer systems, data is often transmitted fromthe sending element at a higher rate than it can be consumed at thereceiving element. In order to facilitate data communication between thesending element and the receiving element, high-speed buffers such asFirst In First Out (FIFO) devices are used.

[0005] A FIFO device typically comprises a plurality of seriallyarranged storage cells (or memory locations) which are sequentiallywritten into and read from. A write address pointer holds the writebinary address of the storage cell into which data will be writtenduring the next write operation, and a read address pointer holds theread binary address of the storage cell from which data will be readduring the next read operation.

[0006]FIG. 1 illustrates a conventional FIFO device 100. FIFO device 100comprises a FIFO memory element 101, a write address circuit 103, awrite multiplexer 105, a read address circuit 107, and a readmultiplexer 109. Moreover, memory element 101 may be a Random AccessMemory (RAM) in which reading and writing of data may be performedsimultaneously and comprises a capacity of N words. While a readpermission signal (RE) is asserted, data (RDATA) is read from an addressdesignated by a read address (RADR) on a word-by-word basis at a clocktiming of a clock signal (CLK). Similarly, while a write permissionsignal (WE) is asserted, data (WDATA) is written into an addressdesignated by a write address (WADR) on a word-by-word basis at a clocktiming of the clock signal CLK.

[0007] The read address circuit 107 receives the clock signal CLK andthe read permission signal (RE). While the read permission signal (RE)is asserted, the read address circuit 107 increments the read address(RADR) by one at a clock timing of the clock signal CLK.

[0008] The write address circuit 103 receives the clock signal CLK andthe write permission (WE). While the write permission signal (WE) isasserted, the write address circuit 103 increments the write address(WADR) by one at a clock timing of the clock signal CLK.

[0009] The conventional FIFO control circuit illustrated in FIG. 1 maybe used to facilitate the data rate discrepancy between the sendingelement and the receiving element. However, such conventional FIFOcontrol circuits do not detect or discard obsolete data stored in theFIFO memory, and therefore require additional read cycles to processobsolete data that need not be read.

SUMMARY OF INVENTION

[0010] Accordingly, the present invention provides a dynamic FIFO flowcontrol circuit and a method of performing. In one embodiment of thepresent invention, the flow control circuit detects that the next one ormore data entries in a FIFO memory contain obsolete data. The flowcontrol circuit stores the address of the next valid read pointer in aregister, the address of the next valid read pointer is then loaded fromthe register to read the next data entry during the next read operation.

[0011] The FIFO flow control circuit of the present invention allows fordetection of obsolete data entries in the FIFO memory and thereby savesreading cycles by skipping the read pointer address to the next validdata entry rather than reading from obsolete data entries.

BRIEF DESCRIPTION OF DRAWINGS

[0012] The accompanying drawings that are incorporated in and form apart of this specification illustrate embodiments of the invention andtogether with the description, serve to explain the principles of theinvention:

[0013]FIG. 1 is a prior art architectural diagram illustrating aconventional FIFO memory circuit.

[0014]FIG. 2 is an architectural diagram illustrating a dynamic FIFOflow control circuit in accordance to one embodiment of the presentinvention.

[0015]FIG. 3 is a flow chart diagram illustrating a read cycle of a FIFOflow control circuit in accordance to one embodiment of the presentinvention.

[0016]FIG. 4 is an architectural diagram illustrating a control circuitcomprising a FIFO device working in conjunction with a TRI_PTR FIFO anda Header FIFO in order to detect and avoid obsolete data entry readsaccording to one embodiment of the present invention.

[0017]FIG. 5 is a diagram illustrating a TRI_PTR FIFO comprising fiveaddress pointers according to one embodiment of the present invention.

[0018]FIG. 6 is a diagram illustrating a TRI_PTR FIFO comprising threeaddress pointers according to a second embodiment of the presentinvention.

[0019]FIG. 7 is a flow diagram illustrating a detailed write operationof the architectural diagram shown in FIG. 4 according to one embodimentof the present invention.

[0020]FIG. 8 is a flow diagram illustrating a detailed read operation ofthe architectural diagram shown in FIG. 4 according to one embodiment ofthe present invention.

DETAILED DESCRIPTION OF EXEMPLARY EMBODIMENT(S)

[0021] The following description is presented to enable one of ordinaryskill in the art to make and use the invention and is provided in thecontext of a patent application and its requirements. In the followingdescription, specific nomenclature is set forth to provide a thoroughunderstanding of the present invention. It will be apparent to oneskilled in the art that the specific details may not be necessary topractice the present invention. Furthermore, various modifications tothe embodiments will be readily apparent to those skilled in the art andthe generic principles herein may be applied to other embodiments. Thus,the present invention is not intended to be limited to the embodimentsshown but is to be accorded the widest scope consistent with theprinciples and features described herein.

[0022]FIG. 2 illustrates a FIFO device 200 according to one embodimentof the present invention. FIFO device 200 comprises: a FIFO memoryelement denoted 201, a write control circuit denoted 202A, and a readcontrol circuit denoted 202B. Memory element 201 may be a Random AccessMemory (RAM) in which reading and writing of data may be performedsimultaneously and comprises a capacity of N words.

[0023] Write control circuit 202A further comprises a write addresscircuit denoted 203 and a write multiplexer denoted 205. While a writepermission signal (WE) is asserted, data (WDATA) is written into anaddress designated by a write address (WADR) on a word-by-word basis ata clock timing of a clock signal CLK.

[0024] During a write operation, write control circuit 202A receives theclock signal CLK and the write permission (WE). While the writepermission signal (WE) is asserted, the write address circuit 203increments the write address (WADR) by one at a clock timing of theclock signal CLK. Moreover, while the write permission signal (WE) andthe clock signal CLK are asserted, multiplexer 205 selects input “1” inorder to increment the write address (WADR) by one.

[0025] Read control circuit 202B further comprises a read addresscircuit denoted 207, a first multiplexer 209 and a second multiplexerdenoted 206. While a read permission signal (RE) is asserted, data(RDATA) is read from an address designated by a read address (RADR) on aword-by-word basis at a clock timing of the clock signal CLK.

[0026] Moreover, read control circuit 202B functions in two modesregulated by multiplexer 206. FIG. 3 illustrates the functional steps ofread control 202B. At step 301, the RE and CLK signals are asserted tosignify a read operation request. A clean_act signal (shown in FIG. 2)is checked in step 303. An asserted clean_act signal indicates that thenext one or more data entries to be read are obsolete such as ODATA1,ODATA2, and ODATA3 shown in FIG. 2. Accordingly, if the clean_act signalis asserted, a next_valid (shown in FIG. 2) pointer is selected in step305. An address of the next valid data entry held by the next_validpointer is then loaded and designated as the RADR in step 307. Referringnow back to step 303, if the clean_act signal is not asserted, a readoperation is performed at the read address RADR, and RADR issubsequently incremented by one in step 308. Moreover, while the readpermission signal (RE) and the clock signal CLK are asserted,multiplexer 209 selects input “1” in order to increment the read address(RADR) by one.

[0027]FIG. 4 is an architectural diagram illustrating a control circuitcomprising a FIFO device such as FIFO device 200 working in conjunctionwith two conventional FIFO devices TRI_PTR FIFO and Header FIFOaccording to one embodiment of the present invention. Moreover, FIG. 4illustrates components comprising: an arithmetic logic unit (ALU)denoted 401, a controller denoted 429, a rejected/culled registerdenoted 433, a header_processed register denoted 419, a first flip flopdenoted DFF0, a second flip flop denoted DFF1, a third flip flop denotedDFF2, a fourth flip flop denoted DFF3, a fifth flip flop denoted DFF4, asixth flip flop denoted DFF5, a multiplexer denoted 415, an incomingdata entry denoted 417, a FIFO device 200 such as shown in FIG. 2, aTRI_PTR FIFO denoted 427, a comparator denoted 421, a flip flop denoted423, and a Header FIFO denoted 425.

[0028] TRI_PTR FIFO 427 and Header FIFO 425 are used in conjunction withFIFO device 200 in order to detect and avoid obsolete data reads in FIFOdevice 200. Moreover, the interaction between TRI_PTR FIFO 427, HeaderFIFO 425, and FIFO device 200 is described in detail in FIGS. 5, 6, 7,and 8 below.

[0029] FIFO device 200 may be used to store various types of data. Inthe embodiment shown in FIG. 4, FIFO device 200 receives and storesgraphics related data entries. For graphic applications, an image may berepresented by numerous primitives, such as triangles. Furthermore, eachtriangle may be represented by vertices wherein each vertex hascoordinates (X, Y, Z, W), color attributes (e.g. specular, ARGB, DiffuseARGB, etc.), and texture parameters (U,V). Vertex data such ascoordinates, attributes, and texture parameters for each triangle aresegmented into data entries such as incoming data entry 417 and storedinto FIFO device 200.

[0030] For each triangle, a header entry is processed and the trianglemay be rejected or culled based on the header data contained in theheader entry. However, due to various latencies such as pipelinelatency, one or more data entries such as an attribute data entry ortexture data entry associated with a rejected or culled triangle may bestored in FIFO device 200 before the header is processed. The controlcircuit shown in FIG. 4 keeps track of the base address of data entriesfor each triangle in order to avoid data entry reads of a rejected orculled triangle.

[0031] In the embodiment shown in FIG. 4, an incoming valid data entryis divided into various segments. Incoming valid entry 417, shown inFIG. 4, comprises a valid bit to signal the validity of the incomingdata, an is_header bit for distinguishing a header valid entry from anattribute or texture valid entry, an is_last_entry bit fordistinguishing the last valid entry of each triangle, a TRI_ID segmentto distinguish data entries of distinct triangles, and a payload denoteddata/header comprising triangle data such as header data or attributedata.

[0032]FIG. 7 is a flow chart diagram illustrating functional steps for awrite operation in a control circuit such as shown in FIG. 4. In step701, a valid entry is received at a control circuit such as shown inFIG. 4. In step 703, the header status of the valid entry is determinedaccording to a segment of the valid entry such as the is_header bitshown in FIG. 4. If the valid entry contains valid header data, in step705, the valid entry is written into a conventional FIFO such as HeaderFIFO 425. The header entry written into the conventional FIFO comprisesthe data/header segment as well as identification segments such asTRI_ID, is_header, is_last, etc. The header entry is written into theHeader FIFO 425 by enabling a write enable signal Header_WE as shown inFIG. 4. Furthermore, in step 705, the data/header portion of the headerentry is read from Header FIFO 425 into an arithmetic logic unit (ALU)such as ALU 401 shown in FIG. 4, and an identification tag such asTRI_ID is read from Header FIFO 425 into a controller such as controller429. The data and the identification tag are read from Header FIFO 425by enabling a read enable signal Header_RE as shown in FIG. 4.

[0033] The number of triangles and associated data stored in FIFO device200 depend on the number of pipelines that input to FIFO device 200.TRI_ID identifies the triangle with which each incoming data entry isassociated, and controller 429 schedules the order in which ALU 401processes the data ALU 401 receives. For example, if ALU 401 receivesdata (RDATA) from FIFO 200 at the same time as it receives header datafrom Header FIFO 425, controller 429 may decide that header data takespriority to RDATA and informs ALU 401 to process the header data priorto RDATA. Controller 429 sends a Mode signal to ALU 401 to indicate thetype (i.e. header, attribute, etc.) of data ALU 401 is receiving.

[0034] In the embodiment shown in FIG. 4, six pipelines are used inconjunction with FIFO device 200, and data associated with six distincttriangles may be processed by ALU 401 simultaneously. Furthermore, eachtriangle may either be rendered or rejected/culled. If a triangle is tobe rejected/culled, a bit stored in a flip flop corresponding to thetriangle is set to logical one. In the embodiment shown in FIG. 4, sixdistinct triangles may be processed by ALU 401 simultaneously, and eachof the six triangles corresponds to flip flops DFF0, DFF1, DFF2, DFF3,DFF4, and DFF5 respectively, wherein each flip flop stores a bit thatindicates whether the corresponding triangle is rejected/culled.Referring now back to step 705, in addition to writing the header datato Header FIFO 425 and ALU 401, a bit stored in the flip flopcorresponding to the triangle is set to logical zero to indicate thatthe triangle has not yet been rejected or culled. Furthermore, thecorresponding flip flop is identified by matching an information segmentof the valid entry such as TRI_ID shown in FIG. 4 with one of the flipflops DFF0, DFF1, DFF2, DFF3, DFF4, and DFF5.

[0035] In step 707, the header is processed in ALU 401 and a bit inheader_processed register 419 corresponding to TRI_ID of the valid entryis set to logical one in step 709 when the header data is processed.Subsequently in step 711, ALU 401 determines if the triangle is rejectedor culled according to the header data. If the triangle is rejected orculled (i.e. not to be rendered), ALU 401 sets a culled bit stored inrejected/culled register 433 to one, wherein the bit corresponds to therejected/culled triangle. Furthermore, the culled bit triggers the flipflop corresponding to the rejected/culled triangle to set its content tological one in step 713. In an illustrated example, ALU 401 processesthe header of triangle0 and determines that triangle0 isrejected/culled. ALU 401 then sets the bit culled0 stored in register433 to one. Culled0 triggers DFF0 to set its content to one, indicatingthat the triangle is rejected/culled. Conversely, if the triangle is notrejected or culled, the bit stored in the flip flop corresponding to thetriangle is set to logical zero in step 717.

[0036] Referring now back to step 703 of FIG. 7. If the valid entry isnot a header, in step 706, a bit stored in a flip flop corresponding toTRI_ID of the valid entry is checked to determine if the trianglecorresponding to the valid entry is rejected or culled. If the trianglecorresponding to the valid entry is rejected or culled, in step 708, thevalid entry is prevented from being written to FIFO device 200.

[0037] Conversely, if the triangle corresponding to the valid entry isnot rejected or culled, in step 710, the current TRI_ID is compared tothe TRI_ID of the previous valid entry to determine if data associatedwith a new triangle is being written to FIFO device 200. Comparator 421takes the current TRI_ID as one of two inputs, the current TRI_ID isalso coupled to a flip flop 423 and the output of flip flop 423 (i.e.TRI_ID of the valid entry processed in the previous clock cycle) iscoupled to the second input of comparator 421. Comparator 421 comparesthe current triangle ID to the previous triangle ID and outputs a signalto TRI_PTR FIFO 427, wherein the signal indicates whether a new triangleis being written to FIFO device 200.

[0038] Referring now back to step 710 of FIG. 7, if the output ofcomparator 421 signifies that the current triangle ID equals to theprevious triangle ID, indicating the current valid entry and theprevious valid entry are associated with the same triangle; the dataportion of the valid entry along with additional parameter informationsuch as TRI_ID and is_last_entry are then written into FIFO device 200in step 714.

[0039] If the output of comparator 421 signifies that data associatedwith a new triangle is being written to FIFO device 200, TRI_PTR FIFO427 is updated and the data portion of the valid entry along withadditional parameter information such as TRI_ID and is_last_entry arewritten into FIFO device 200 in step 712.

[0040] TRI_PTR FIFO 427 is a conventional FIFO device comprising storagecapacity of M words wherein M equals to the number of pipelines used. Asan illustrative example, TRI_PTR FIFO 427 shown in FIG. 5 comprises astorage capacity of six data words. Furthermore, when TRI_PTR FIFO 427is updated such as it is in step 712 of FIG. 7, the base address of thenew triangle base_addr is written into the address held in write pointerWP (shown in FIG. 5), and the WP is then incremented by one to point tothe next data word.

[0041] In one embodiment of the present invention shown in FIG. 5,TRI_PTR FIFO 427 comprises five data entries wherein each data entrycomprises an address corresponding to the base address of triangles TR1,TR2, TR3, TR4, and TR5 respectively. TRI_PTR FIFO 427 shown in FIG. 5indicates that either all six triangles will be rendered and thereforenot rejected/culled, or some data entries associated with one or morerejected/culled triangles were written to FIFO device 200 before thecorresponding headers were processed.

[0042] In an alternative embodiment of the present invention shown inFIG. 6, TRI_PTR FIFO 427 comprises only three data entries wherein eachdata entry comprises an address corresponding to the base address oftriangles TR2, TR3, and TR5, respectively. TRI_PTR FIFO 427 shown inFIG. 6 indicates that at least TR1 and TR4 are rejected/culled and thecorresponding headers were processed before any data associated witheither triangle was written to FIFO device 200.

[0043]FIG. 8 is a flow chart diagram illustrating functional steps for aread operation in a control circuit such as shown in FIG. 4. In step801, the control circuit extracts the identification of the data entryto be read, the identification may be an ID tag such as TRI_ID storedalong with the data in FIFO device 200. Moreover, the identificationinformation extracted in step 801 identifies the triangle with which thedata entry is associated.

[0044] In step 803, a bit corresponding to the extracted triangle IDTRI_ID in a header_processed register such as register 419 shown in FIG.4 is checked along with a bit stored in a flip flop corresponding to thetriangle ID TRI_ID. For example, for a TRI_ID of 0, HP0 and the bitstored in DFF0 are checked in step 803. If the corresponding bit in theheader_processed register indicates that the header for the triangle hasyet been processed (i.e. header_processed bit=logical zero) in ALU 401,in step 805, the read operation is not performed and step 803 isrepeated until the corresponding header has been processed. If theheader has been processed in step 803 and the triangle isrejected/culled as indicated by the bit stored in the corresponding flipflop, in step 809, controller 429 activates (i.e. set to logical one)two signals clean_act (shown in FIG. 2 and FIG. 4) andlast_read_clean_act (shown in FIG. 4).

[0045] In step 811, the read address held by RP (shown in FIG. 5) isincremented by one and RADR (shown in FIG. 2 and FIG. 4) is set to theaddress held by the next_valid (shown in FIG. 2 and FIG. 4) pointer.When the signal last_read_clean_act is activated, TRI_PTR FIFO 427increments a read address held by a read pointer such as RP (shown inFIG. 6) to the next data entry in TRI_PTR FIFO 427. Moreover, when theclean_act signal is activated, TRI_PTR FIFO 427 performs a readoperation and outputs the read data to the next_valid pointer (shown inFIG. 2 and FIG. 4).

[0046] Referring now back to step 807. If the triangle is determined asnot rejected or culled after the header is processed in ALU 401, in step810, a verification is made to check if the data entry to be read is thelast entry of the triangle associated with the data entry. If the dataentry read is not the last entry of the triangle associated with thedata entry, in step 816, a read operation is performed in FIFO device200 and RADR (shown in FIG. 2) is incremented by one. The data (RDATA)read from FIFO device 200 is output to ALU 401 and identification tagssuch as TRI_ID, is_header, and is_last_entry are output to controller429 via output 431 as shown in FIG. 4.

[0047] Conversely, if the data entry read is the last entry of thetriangle associated with the data entry, in step 812, a read operationis performed in FIFO device 200 and controller 429 activates (i.e. setto logical one) signal last_read_clean_act (shown in FIG. 4). The dataread by FIFO device 200 is output to ALU 401 and identification tagssuch as TRI_ID, is_header, and is_last_entry are output to controller429 via output 431 as shown in FIG. 4. Furthermore, when the signallast_read_clean_act is activated, TRI_PTR FIFO 427 increments a readaddress held by a read point such as RP (shown in FIG. 6) to the nextdata entry in TRI_PTR FIFO 427. Subsequently in step 814, RADR (shown inFIG. 2) and the reader address held by RP (shown in FIG. 5) are eachincremented by one.

[0048] The foregoing descriptions of specific embodiments of the presentinvention have been presented for purposes of illustration anddescription. They are not intended to be exhaustive or to limit theinvention to the precise forms disclosed, and obviously manymodifications and variations are possible in light of the aboveteaching. The embodiments were chosen and described in order to bestexplain the principles of the invention and its practical application,to thereby enable others skilled in the arts to best utilize theinvention and various embodiments with various modifications as aresuited to the particular use contemplated. It is intended that the scopeof the invention be defined by the claims appended hereto and theirequivalents.

[0049] For example, FIG. 7 illustrates a single write operation. Inanother embodiment of the present invention, pipelining is used inconjunction with a control circuit such as shown in FIG. 4 and severaldata entries may be held in numerous threads simultaneously, the orderin which the data entries are processed is scheduled by a controllersuch as controller 429.

[0050] Moreover, valid entry 417 shown in FIG. 4 comprises fivesegments. In another embodiment of the present invention, the validentry may be divided into greater or fewer segments according to desireddesign parameters. FIG. 4 illustrates six pipelines, in anotherembodiment of the present invention, a greater or fewer number ofpipelines may be used.

[0051] Bit signals such as last_read_clean_act, is_header,is_last_entry, valid, clean_act, bits stored in header_processedregister, and bits stored in DFF0, DFF1, DFF2, DFF3, DFF4, and DFF5 areset to logical one to correspond to a TRUE state and set to logical zeroto correspond to a FALSE state, various representations of the twostates may be used without altering the essence of the invention.

I claim:
 1. A method of optimally performing read operations in a firstFIFO device with a control circuit coupled to the first FIFO device, themethod comprising: a) detecting an asserted read enable signal at thefirst FIFO device, wherein a first read pointer holds an address to thedata entry to be read in a first FIFO memory in the first FIFO device;b) detecting one or more obsolete data entries starting at the addressheld by the first read pointer; and c) loading the address of the nextvalid data entry into the first read pointer.
 2. The method of claim 1,further comprising the step of detecting an asserted write enable signalat the first FIFO device, wherein a first write pointer holds an addressto be written to in the first FIFO memory.
 3. The method of claim 2,further comprising the step of receiving a valid entry at the controlcircuit.
 4. The method of claim 3, wherein the valid entry comprisesgraphics related data.
 5. The method of claim 4, wherein the valid entrycomprises data associated with a triangle.
 6. The method of claim 5,further comprising the step of determining whether the received validentry is a header entry.
 7. The method of claim 6, wherein the receivedvalid entry is a header entry.
 8. The method of claim 7, wherein theheader entry comprises an identification tag for identifying thetriangle.
 9. The method of claim 8, further comprising the step ofwriting the received header entry into a second FIFO device, setting abit stored in a flip flop to logical zero wherein the flip flopcorresponds to the triangle, sending the header data of the receivedheader entry to an arithmetic logic unit (ALU) wherein the ALU isincluded in the control circuit, and sending the identification tag to acontroller coupled to the ALU.
 10. The method of claim 9, furthercomprising the step of processing the header data sent to the ALU. 11.The method of claim 10, further comprising the step of setting a bit ina register coupled to the ALU to logical one, wherein the bitcorresponds to the triangle.
 12. The method of claim 11, furthercomprising the step of determining whether the triangle is rejected orculled.
 13. The method of claim 12, wherein the triangle is rejected orculled.
 14. The method of claim 13, further comprising the step ofsetting the bit stored in the flip flop associated with the triangle tological one.
 15. The method of claim 12, wherein the triangle associatedwith the header entry is not rejected or culled.
 16. The method of claim15, further comprising the step of setting the bit stored in the flipflop associated with the triangle to logical zero.
 17. The method ofclaim 6, wherein the received valid entry is not a header entry.
 18. Themethod of claim 17, wherein the valid entry comprises a firstidentification tag for identifying the triangle with which the receivedvalid entry is associated.
 19. The method of claim 18, wherein the validentry comprises a second identification tag for differentiating the lastvalid entry associated with the triangle.
 20. The method of claim 19,further comprising the step of determining whether the triangle isrejected or culled.
 21. The method of claim 20, wherein the triangle isrejected or culled.
 22. The method of claim 21, wherein the valid entryis not written into the first FIFO device.
 23. The method of claim 20,wherein the triangle is not rejected or culled.
 24. The method of claim23, further comprising the step of determining whether a new triangle isbeing written to the first FIFO device.
 25. The method of claim 24,wherein the determining step further comprises the step of comparing thefirst identification tag of the current valid entry to a thirdidentification tag of the previous valid entry wherein the thirdidentification identifies the triangle with which the previouslyreceived valid entry is associated.
 26. The method of claim 25, whereinthe new triangle is being written to the first FIFO device.
 27. Themethod of claim 26, further comprising the step of writing the validentry to the first FIFO memory at the address held by the first writepointer, and updating a second FIFO device wherein the second FIFOdevice is coupled to the first FIFO device.
 28. The method of claim 27,wherein the updating step further comprising writing the address held bythe first write pointer into the second FIFO device and incrementing asecond write pointer by one wherein the second write pointer holds anaddress to be written to a second FIFO memory of the second FIFO device.29. The method of claim 25, wherein the new triangle is not beingwritten to the first FIFO device.
 30. The method of claim 29, furthercomprising the step of writing the valid entry to the first FIFO memoryat the address held by the first write pointer.
 31. The method of claim2, wherein the valid entry to be read is graphics related data.
 32. Themethod of claim 31, wherein the valid entry comprises data associatedwith a triangle.
 33. The method of claim 32, wherein the detecting stepb) further comprising the step of checking a first identification tag ofthe date entry, wherein the first identification tag of the valid entryidentifies the triangle.
 34. The method of claim 33, further comprisingthe step of checking a bit corresponding to the triangle in a registerto verify whether a header entry of the triangle has been processed. 35.The method of claim 34, wherein the header entry of the triangle has notbeen processed.
 36. The method of claim 35, further comprising the stepof repeating the checking step of claim
 34. 37. The method of claim 34,wherein the header entry of the triangle has been processed.
 38. Themethod of claim 37, further comprising the step of determining whetherthe triangle is rejected or culled.
 39. The method of claim 38, whereinthe triangle is rejected or culled.
 40. The method of claim 39, furthercomprising the step of setting a first signal to logical one, whereinthe first signal signifies to the first FIFO device that the next one ormore data entries are obsolete.
 41. The method of claim 40, furthercomprising the step of performing a read operation in a second FIFOdevice coupled to the first FIFO device wherein the output of the readoperation is loaded into the first read pointer of the first FIFOdevice, and incrementing the address held by a second read pointer byone wherein the second read pointer holds an address in the second FIFOdevice.
 42. The method of claim 38, wherein the triangle is not rejectedor culled.
 43. The method of claim 42, further comprising the step ofdetermining if the data entry to be read is the last entry of thetriangle.
 44. The method of claim 43, wherein the determining stepfurther comprising the step of checking a second identification tag ofthe data entry, wherein the second identification tag differentiates thelast data entry of the triangle.
 45. The method of claim 44, wherein thedata entry to be read is the last entry of the triangle.
 46. The methodof claim 45, further comprising the step of reading the data entry fromthe first FIFO memory at the address held by the first read pointer. 47.The method of claim 46, further comprising the step of incrementing byone the address held by the first read pointer, and incrementing theaddress held by a second read pointer by one wherein the second readpointer holds an address in a second FIFO device coupled to the firstFIFO device.
 48. The method of claim 44, wherein the data entry to beread is not the last entry of the triangle.
 49. The method of claim 48,further comprising the step of reading the data entry from the firstFIFO memory at the address held by the first read pointer, wherein thedata of the data entry is read into an algorithmic logic unit (ALU)included in the control circuit and identification tags of the dataentry are read into a controller coupled to the ALU.
 50. The method ofclaim 49, further comprising the step of incrementing by one the addressheld by the first read pointer.
 51. A method of optimally performingread operations in a first FIFO device with a control circuit coupled tothe first FIFO device, the method comprising: a) detecting an assertedread enable signal at the first FIFO device, wherein a first readpointer holds an address to the data entry to be read in a first FIFOmemory in the first FIFO device; b) checking a first identification tagof the data entry to be read; c) checking whether a header entrycorresponding to the first identification tag has been processed; d)iterating step c) until the header entry corresponding to the firstidentification tag has been processed; e) checking whether a graphicsprimitive corresponding to the first identification tag is rejected orculled; f) if the primitive is rejected or culled, signifying to thefirst FIFO device that one or more obsolete data entries starting at theaddress held by the first read pointer have been detected; and g)loading the address of the next valid data entry into the first readpointer.
 52. The method of claim 51, wherein step g) further comprisingthe step of performing a read operation in a second FIFO device coupledto the first FIFO device wherein the output of the read operation isloaded into the first read pointer of the first FIFO device, andincrementing the address held by a second read pointer by one whereinthe second read pointer holds an address in the second FIFO device. 53.The method of claim 52, wherein the primitive corresponding to the firstidentification tag is rejected or culled.
 54. The method of claim 53,further comprising the step of determining if the data entry to be readis the last entry of the primitive.
 55. The method of claim 54, whereinthe determining step further comprising the step of checking a secondidentification tag of the data entry, wherein the second identificationtag differentiates the last data entry of the primitive.
 56. The methodof claim 55, wherein the data entry to be read is the last entry of theprimitive.
 57. The method of claim 56, further comprising the step ofreading the data entry from the first FIFO memory at the address held bythe first read pointer, wherein the data of the data entry is read intoan algorithmic logic unit (ALU) included in the control circuit andidentification tags of the data entry are read into a controller coupledto the ALU.
 58. The method of claim 57, further comprising the step ofincrementing by one the address held by the first read pointer, andincrementing the address held by a second read pointer by one whereinthe second read pointer holds an address in the second FIFO device. 59.The method of claim 55, wherein the data entry to be read is not thelast entry of the primitive.
 60. The method of claim 59, furthercomprising the step of reading the data entry from the first FIFO memoryat the address held by the first read pointer, wherein the data of thedata entry is read into an algorithmic logic unit (ALU) included in thecontrol circuit and identification tags of the data entry are read intoa controller coupled to the ALU.
 61. The method of claim 60, furthercomprising the step of incrementing by one the address held by the firstread pointer.
 62. An optimal FIFO control circuit comprising: a firstFIFO device having a first FIFO memory, a first write pointer holding afirst write address, and a first read pointer holding a first readaddress; and a second FIFO device coupled to the first FIFO device, thesecond FIFO device having a second FIFO memory, a second write pointerholding a second write address, and a second read pointer holding asecond read address.
 63. The control circuit of claim 62, furthercomprising a first input coupled to the first FIFO device, wherein thefirst input signifies that the next one or more data entries, startingat the first read address, are obsolete.
 64. The control circuit ofclaim 63, further comprising a second input coupled to the first FIFOdevice, wherein the second input comprises data written to the firstFIFO memory.
 65. The control circuit of claim 64, further comprising afirst data connection from the second FIFO device to the first FIFOdevice, wherein the first data connection comprises an address to thenext valid entry in the first FIFO device.
 66. The control circuit ofclaim 65, further comprising a third input coupled to the first FIFOdevice, wherein the third input comprises a first read enable signalsignifying a read operation request.
 67. The control circuit of claim66, further comprising a fourth input coupled to the first FIFO device,wherein the fourth input comprises a first write enable signalsignifying a write operation request.
 68. The control circuit of claim67, further comprising a first output coupled to the first FIFO device,wherein the first output comprises data read from the first FIFO memoryread operations.
 69. The control circuit of claim 68, further comprisinga second data connection from the first FIFO device to the second FIFOdevice, wherein the second data connection comprises data written to thesecond FIFO memory during write operations.
 70. The control circuit ofclaim 69, further comprising a fifth input coupled to the second FIFOdevice, wherein the fifth input comprises a second read enable signalsignifying a read operation request.
 71. The control circuit of claim70, further comprising a sixth input coupled to the second FIFO device,wherein the sixth input comprises a second write enable signalsignifying a write operation request.
 72. An optimal FIFO controlcircuit comprising: a first FIFO device having a first FIFO memory, afirst write pointer holding a first write address, and a first readpointer holding a first read address; a second FIFO device coupled tothe first FIFO device, the second FIFO device having a second FIFOmemory, a second write pointer holding a second write address, and asecond read pointer holding a second read address; a controller coupledto the first FIFO device and the second FIFO device; and a third FIFOdevice coupled to the controller, the third FIFO device having a thirdFIFO memory, a third write pointer holding a third write address, and athird read pointer holding a third read address.
 73. The control circuitof claim 72, further comprising a first data connection from thecontroller to the first FIFO device, wherein the data connectioncomprising data that indicates whether the next one or more dataentries, starting at the first read address, are obsolete.
 74. Thecontrol circuit of claim 73, further comprising a first input coupled tothe first FIFO device, wherein the first input comprises data written tothe first FIFO memory.
 75. The control circuit of claim 74, furthercomprising a second data connection from the second FIFO to the firstFIFO device, wherein the second data connection comprises an address tothe next valid entry in the first FIFO device.
 76. The control circuitof claim 75, further comprising a third data connection from thecontroller to the first FIFO device, wherein the third data connectioncomprises a first read enable signal signifying a read operationrequest.
 77. The control circuit of claim 76, further comprising asecond input coupled to the first FIFO device, wherein the second inputcomprises a first write enable signal signifying a write operationrequest.
 78. The control circuit of claim 77, further comprising afourth data connection from the first FIFO device to the controller,wherein the fourth data connection comprises data read from the firstFIFO memory read operations.
 79. The control circuit of claim 78,further comprising a fifth data connection from the first FIFO device tothe second FIFO device, wherein the fifth data connection comprises datawritten to the second FIFO memory during write operations.
 80. Thecontrol circuit of claim 79, further comprising an sixth data connectioncoupled from the controller to the second FIFO device, wherein the sixthdata connection comprises a second read enable signal signifying a readoperation request.
 81. The control circuit of claim 80, furthercomprising a third input coupled to the second FIFO device, wherein thethird input comprises a second write enable signal signifying a writeoperation request.
 82. The control circuit of claim 81, furthercomprising a seventh data connection from the controller to the thirdFIFO device, wherein the seventh data connection comprises a third readenable signal signifying a read operation request.
 83. The controlcircuit of claim 82, further comprising a fourth input coupled to thethird FIFO device, wherein the fourth input comprises a third writeenable signal signifying a write operation request.
 84. The controlcircuit of claim 83, further comprising an eighth data connection fromthe third FIFO device to the controller, wherein the eighth dataconnection comprises data read from the third FIFO memory readoperations.
 85. The control circuit of claim 84, further comprising afifth input coupled to the third FIFO device, wherein the fifth inputcomprises data written to the third FIFO memory